A measuring apparatus detects a control unit variable of a control unit program which is executed in a control apparatus by a control unit processor. The control apparatus can be an engine controller for a motor vehicle, an embedded system or the like, which can be used to control actuators, for example electric motors, controllers or the like. The control unit processor uses a memory data connection with a detection device for detecting data which are transmitted on the memory data connection. The detecting device, for example, is a temperature sensor, a measuring transducer or the like that is connected to the control apparatus. The control unit processor executes a control program, for example in order to monitor the actuator, to control injection quantities of an internal combustion engine or the like.
The control unit processor is connected to a control unit memory of the control unit in order to store, for example, control parameters and other used, measured and/or calculated variables there. Thus, the control unit processor writes the control unit variable to a control unit memory. The control unit variable, for example, is a measured value, a temporary controller value, an output value at an actuator or the like. The variable may also comprise a program variable used by a program function.
The measuring apparatus has a buffer memory, to which, in a process herein also referred to as recording or tracing, the measuring apparatus writes the data which have been transmitted in memory access operations, i.e., when using the memory data connection, for transmission to a mapping memory, herein also referred to as a mirror memory. The mirror memory is thus made to hold a memory map of at least part of the control unit memory.
Recording the memory access operations of the control unit processor can be accomplished in multiple ways. In the case of microprocessors without internal peripherals and memories, it is conventional practice to record the external address/data bus and some control signals. The prerequisite for this so-called bus trace method is physical access to the memory interface of the control apparatus. Adapters which tap off the signals either directly from the control unit processor or directly from the memory module are typically used here. The signals may also be tapped off on the path between the control unit processor and the memory using Press-On adapters for conductor track pads or connectors. If a physical connection is possible in this manner, all memory access operations can be recorded and the program flow and all data access operations can be determined therefrom.
There are restrictions if the control unit processor is provided with a cache or internal RAM. In this case, the situation may occur in which no bus cycle appears on the external bus interface for a long period of time because all data required are already present in the internal memory and are executed there. In this case, a trace tool cannot record anything and the program behaviour remains hidden.
However, ever higher integration densities and pricing pressure have resulted in a processor core, cache, peripherals, flash and RAM memories being integrated in a single housing in many processors (system-on-chip). These processors often no longer even have an external memory interface. The bus trace method cannot be used in this case. Therefore, some processor architectures provide a special trace interface on the chip in addition to the debug interface. This trace interface can be used to make the program flow and data trace visible to the outside in compressed form.
A trace bus which has a width of 4, 8 or 16 bits and can be used to transmit program flow data and/or data access operations at a bus frequency of up to 400 MHz in compressed form is usually used as the trace interface. Other options are high-speed serial interfaces in the gigabit/s range with differential low-voltage swing signalling. In this case, the information on the address bus/data bus is transmitted in the manner in which it directly occurs in the CPU core with address and data values. This means that operations to access peripherals, chip-internal flash or RAM memory—in particular also cached operations—can also be recorded.
However, one disadvantage of this trace method is the high bandwidth needed to transmit the trace data. The problem is intensified in multi-core systems since the required bandwidth increases linearly with the number of processors.